1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus is configured to receive data, store data, and output the stored data all in synchronization with a clock.
FIG. 1 shows a conventional semiconductor memory apparatus. The conventional semiconductor memory apparatus includes first to fourth sampling units 11, 12, 13 and 14, and a data output unit 20.
The first sampling unit 11 is inputted with a first clock CLK0, a second clock CLK1, and first input data D_in<0>. The first sampling unit 11 outputs the first input data D_in<0> as first sampling data D_p<0> when both the first clock CLK0 and the second clock CLK1 are low levels. The first clock CLK0 and the second clock CLK1 have a phase difference of ¼ cycle. The first sampling unit 11 includes first to fifth transistors P1, P2, N1, N2 and N3. The first transistor P1 has a gate to which a ground terminal VSS is electrically coupled, and a source which is applied with an external voltage VDD. The second transistor P2 has a gate which is inputted with the first input data D_in<0>, and a source to which the drain of the first transistor P1 is electrically coupled. The third transistor N1 has a gate which is inputted with the first clock CLK0, a drain which is electrically coupled to the drain of the second transistor P2, and a source which is electrically coupled to the ground terminal VSS. The fourth transistor N2 has a gate which is inputted with the second clock CLK1, a drain which is electrically coupled to the drain of the second transistor P2, and a source which is electrically coupled to the ground terminal VSS. The fifth transistor N3 has a gate which is inputted with the first input data D_in<0>, a drain which is electrically coupled to the drain of the second transistor P2, and a source to which is electrically coupled to the ground terminal VSS.
The second sampling unit 12 is inputted with the second clock CLK1, a third clock CLK2, and second input data D_in<1>. The second sampling unit 12 outputs the second input data D_in<1> as second sampling data D_p<1> when both the second clock CLK1 and the third clock CLK2 are low levels. The second clock CLK1 and the third clock CLK2 have a phase difference of ¼ cycle.
The third sampling unit 13 is inputted with the third clock CLK2, a fourth clock CLK3, and third input data D_in<2>. The third sampling unit 13 outputs the third input data D_in<2> as third sampling data D_p<2> when both the third clock CLK2 and the fourth clock CLK3 are low levels. The third clock CLK2 and the fourth clock CLK3 have a phase difference of ¼ cycle.
The fourth sampling unit 14 is inputted with the fourth clock
CLK3, the first clock CLK0, and fourth input data D_in<3>. The fourth sampling unit 14 outputs the fourth input data D_in<3> as fourth sampling data D_p<3> when both the fourth clock CLK3 and the first clock CLK0 are low levels. The fourth clock CLK3 and the first clock CLK0 have a phase difference of ¼ cycle. The second to fourth sampling units 12, 13 and 14 are configured in substantially the same way as the first sampling unit 11 except that signals to be inputted thereto and outputted therefrom are different.
The data output unit 20 outputs the first to fourth sampling is data D_p<0:3> as serial data D_serial.
Operations of the conventional semiconductor memory apparatus will be described below with reference to FIGS. 1 and 2.
The first to fourth clocks CLK0 to CLK3 have a phase difference of ¼ cycle with one another.
During a period in which both the first clock CLK0 and the second clock CLK1 are low levels, the first sampling data D_p<0> is outputted as the serial data D_serial.
During a period in which both the second clock CLK1 and the third clock CLK2 are low levels, the second sampling data D_p<1> is outputted as the serial data D_serial.
During a period in which both the third clock CLK2 and the fourth clock CLK3 are low levels, the third sampling data D_p<2> is outputted as the serial data D_serial.
During a period in which both the fourth clock CLK3 and the first clock CLK0 are low levels, the fourth sampling data D_p<3> is outputted as the serial data D_serial.
The conventional semiconductor memory apparatus operating in this way has substantial power consumption. For example, the first sampling unit 11 outputs the first sampling data D_p<0> during a period in which both the first clock CLK0 and the second clock CLK1 are low levels. To put it in another way, the first sampling unit 11 does not output the first sampling data D_p<0> when any one of the first clock CLK0 and the second clock CLK1 is a high level. In spite of not outputting the first sampling data D_p<0>, that is, not performing an operation, in the first sampling unit 11, the third and fourth transistors N1 and N2 are turned on when any one of the first clock CLK0 and the second clock CLK1 is a high level. At this time, if the level of the first input data D_in<0> is a low level, current flowing in through the first and second transistors P1 and P2 flows out to the ground terminal VSS through the third and fourth transistors N1 and N2.
Since the second to fourth sampling units 12 to 14 are configured in the same way as the first sampling unit 11, they also consume current even while they do not operate.
Such a problem should be solved to realize a semiconductor memory apparatus with low power consumption.